Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Generic Map

Used to define the values of generics. Usually given in an Instance, but may also appear in a configuration.

Syntax

  generic map ([Formal =>] Actual, ...)

  Formal = {either} Name FunctionCall
  Actual = Expression
    

Where

Label: ComponentName port map(-); for-use- port map(-) block-generic(-); ; port-begin-end

Rules

The two forms of syntax (ordered list or explicitly named choices) can be mixed, but the ordered list must come before the named choices.

Things to remember

A generic map does not end with a semicolon!

Example

  architecture Structure of Ent is
    component NAND2
      generic (TPLH, TPHL: TIME := 0 NS);
      port (A, B: in  STD_LOGIC;
            F   : out STD_LOGIC);
    end component;
  begin
    G1: NAND2 generic map (1.9 NS, 2.8 NS)
              port map (N1, N2, N2);
    G2: NAND2 generic map (TPLH => 2 NS, TPHL => 3 NS)
              port map (N4, N5, N6);
  end Structure;
    

See Also

Generic, Instantiation, Block, Configuration